diglot — one IR, two readings

The Verilog you would synthesise and the SMT a solver would see are emitted from the same Design value. They are two denotations of one object, related by mechanised consistency theorems — not two independent translations that happen to agree. Everything below runs in your browser; nothing is sent anywhere.

example loading…

source — .dg

netlist denotation → Verilog

transition-system denotation → SMT-LIB

· source · consistency theorems mechanised in Lean 4 (formal/)